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PC2-5300 / DDR2-
667
PC2-5300 / DDR2-
667
Features
The DDR2 modules are made with the newest 0.1-micron manufacturing process in Fine-Pitch Ball Grid Array (FBGA) chip packages technique, which provides some features, such as Faster data transmission, Lower power consumption, Higher capacity.
240 edge connector pads
Data Rate
667
MHz
SSTL-2 interface
1.8 Voltage +/- 0.1V
Package
FBGA
Capacity
PC2-5300 / DDR2-667 240 Pin DDR2 Unbuffered DIMM
Capacity
Chip Configuration
Chip Type
Non-ECC
With ECC
256MB
32Mx16 (x4)
32Mx16(x5)
DDRII SDRAM
512MB
64Mx8 (x8)
64Mx8(x9)
DDRII SDRAM
1GB
64Mx8(x16)
64Mx8(x18)
DDRII SDRAM
2GB
128Mx8(x16)
128Mx8(x18)
DDRII SDRAM
Specifications
JEDEC Standard
Double Data Rate architecture
Bi-directional Differential Data Stroge (DQS)
MRS cycle with address key programs
*CAS latency: CL3 / 4/ 5
*Burst length: 4, 8
*Burst type: Nibble Sequential & Interleave
2 variations of refresh
*Auto refresh
*Self refresh
Serial Presence Detect support
2 Banks to be operated simultaneously or independently
Date Rate:533MHz
Edge aligned data output, center aligned data input
Bandwidth(max):5.3GB/s
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